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electronics 3 may 98 lsi division KS32C5000 main features of product(KS32C5000) ? 32-bit s-arm7t risc core ? 8 kbytes unified cache / sram(8k cache, 4k/4k cache/sram, or 8k sram mode) ? 2-channel uart ? 2-channel hdlc with dma ? iic bus (simple master) ? 2-channel dma ? 2-channel 32-bit timers ? 10/100mbps ethernet controller(mac) ? interrupt controller ? fast page/edo mode dram controller with cbr refresh and self refresh control ? sram/rom controller ? interrupt controller ? 208 qfp ? m/p : 98. 5(e/s : available) s-arm7t (33mhz) i&d cache mac (10/100m) 2-ch hdlc (with dma) 2-ch timer sram memory controller 2-ch uart iic bus interrupt controller 2-ch dma
electronics 4 may 98 lsi division KS32C5000 main features of product(ks32c5100) ? 32-bit s-arm7t risc core (66mhz@3.3v) ? 8 kbytes unified cache ? 4kbytes sram ? 2-channel uart ? 4-channel hdlc with dedicated dma ? iic bus (simple master) ? 6-channel dma ? 2-channel timers(32-bit) ? watchdog timer(16-bit) ? 10/100mbps ethernet controller(mac) ? host-to-pci bridge unit ? 4 external bus request ? interrupt controller ? edo mode dram/ synchronous dram controller with cbr refresh and self refresh control ? sram/rom/flash controller ? 22 programmable i/o ports ? pll ? 256 qfp ? m/p : 99. 3(e/s : 98. 12) s-arm7t (66mhz) i&d cache (8k) mac (10/100m) 4-ch hdlc 2-ch timer (32-bit) sram (2k) memory controller (edo/sdram) 2-ch uart iic bus interrupt controller 6-ch dma pll host to pci bridge 2-ch uart
electronics 5 may 98 lsi division KS32C5000 application block diagram (ethernet hub/router) cpu bus inter-ric bus remote port(rs-232/v.35) KS32C5000 i2c timer dmac intc uart cache(sram) 8kb ethernet controller mac 10/100mbps bdma hdlc dmac x 2 s-arm7t memory memory ric ric filter module
electronics 6 may 98 lsi division KS32C5000 application block diagram (ethernet switch) cpu bus KS32C5000 i2c timer dmac intc uart cache(sram) 8kb ethernet controller mac 10/100mbps bdma hdlc dmac x 2 s-arm7t memory memory quad mac quad phy quad mac quad phy quad mac quad phy quad mac quad phy switched ethernet engine
electronics 7 may 98 lsi division KS32C5000 application block diagram (cable modem) cpu bus KS32C5000 i2c timer dmac intc uart cache(sram) 8kb ethernet controller mac 10/100mbps bdma hdlc dmac x 2 s-arm7t memory memory cable tuner 3rd mixer adc quam demod. fec rs encode wide band filter 10-bit dac qpsk /qam mod. receiver transmitter from headend to headend pc i/f ethernet 10/100 atm25 pci/usb etc
electronics 8 may 98 lsi division KS32C5000 development supports (demo b/d) KS32C5000 phy rj45 dsub9 x 2 dsub9 x 2 i 2 c bus max 232 max 232 bootrom /flash dram jtag port reset s/w osc (33mhz) embeddedice i/f unit power supply 10/100m ethernet i/f mii i/f ethernet i/f uart0, 1 hdlc i/f
electronics 9 may 98 lsi division KS32C5000 development supports (s/w) ? rtos z psos : available z vxworks : june, 1998 ? drivers z ethernet controller (10/100m mac) z hdlc z uart z dma z iic bus interface z timer z interrupt z etc. ? protocol supports z complete tcp/ip stack and udp, dhcp, bootp, tftp, etc. z snmp mib-ii z web page support ? http client and server ? ftp client and server z internet mail protocol ? pop3 (vxworks) ? smtp (psos, vxworks ) ? optional protocol z ppp z java
electronics 10 may 98 lsi division KS32C5000 strong points ? most suitable solution for networks z cost effective system solution ? built-in ethernet controller(mac) and hdlc ? higher memory efficiency z various peripherals such as iic bus, uart, dma, etc. ? higher performance and lower power consumption z 29mips @ 33mhz, 37mw / mhz ? establishing full line-up from low to high-end z 33mhz to 150mhz ? real time engineering supports z supports easy-to-develop s/w drivers z user friendly development environment z proffer useful document / evaluation board for system development z powerful technical support
electronics 11 may 98 lsi division KS32C5000 comparison table competitor i960cx i960hx mpc821 mpc823 mpc860t rv4640 rv4700 net+arm KS32C5000 ks32c5100* cpu i960 i960 powerpc powerpc powerpc r4000 r4000 arm7tdmi arm7tdmi arm7tdmi cache 4k i-cache 1k d-cache 16k i-cache 8k d-cache mac - - 10m 10m 10/100m - - 10/100m 10/100m 10/100m dma 4-ch - 2-ch 2-ch 16-ch - - 10-ch 6-ch 4-ch 4k i-cache 4k d-cache 8k i-cache 8k d-cache 16k i-cache 16k d-cache hdlc - - 1-ch 1-ch 1-ch - - - 2-ch 4-ch performance 80mips(@40mhz) 150mips(@75mhz) 66mips(@50mhz) 66mips(@50mhz) 52mips(@40mhz) 175mips(@133mhz) 230mips(@175mhz) 15mips 29mips(@33mhz) 58mips(@66mhz) pkg 168pga/196qfp 168pga/208qfp 256bga 256bga 240qfp/255bga 128qfp 179pga 208qfp 208qfp 256qfp 8k i/d-cache 8k i/d-cache
electronics 12 may 98 lsi division KS32C5000 functional descriptions ? system manager ? system memory map ? cache(sram) ? ethernet controller (100/10m mac) ? hdlc ? uart ? timers ? dma ? input / output ? interrupts
electronics 13 may 98 lsi division KS32C5000 system manager ? 16m words addressing range supports ? external 8/16/32-bit bus width supports ? glueless interface for external memory supports z 4 banks of dram supports z 6 banks of rom/sram/flash supports z 4 banks of external i/o z 1 bank of special register ? cbr(cas before ras) refresh, fast page mode, and edo (extended data out) mode for dram access ? programmable bank start/end definition to provide consecutive memory map ? programmable bank size (64k to 4m words for dram/rom/sram, 4k to 16k words for external i/o) ? programmable access cycles for memory bank(2 to 7 cycles) ? one external bus master with bus request/grant pins
electronics 14 may 98 lsi division KS32C5000 system memory map 16m words (sa[25:0] reserved special register bank internal sram external i/o bank 3 external i/o bank 2 external i/o bank 1 external i/o bank 0 dram bank 3 dram bank 2 dram bank 1 dram bank 0 rom/sram/flash bank5 rom/sram/flash bank4 rom/sram/flash bank3 rom/sram/flash bank2 rom/sram/flash bank1 rom/sram/flash bank0 0x0000000 0x3ffffff 16k words(fixed) 0, 4kbytes or 8kbytes(fixed) 4k words(fixed for all i/o banks) 16k ~ 4m words {addr[21:0]} continuous 16kwords for 4 external i/o banks * each bank can be located anywhere in 64m bytes address space
electronics 15 may 98 lsi division KS32C5000 100/10mbps ethernet controller ? cost-effective connection with external ric/ethernet backbone ? buffered dma engine using burst mode ? bdma tx/rx buffer(256bytes/256bytes) ? mac tx/rx fifo(80bytes/16bytes) retransmit after collision without dma request. handle dma latency ? data allignment logic ? endian translation ? supports old/new media compatible with existing 10mbps networks ? 100/10mbps operations ? full ieee802.3/u compatible ? modified mii / modified 7-wire interface ? station management signaling external physical layer configuration and link negotiation ? on chip cam(21 addresses) ? full duplex mode / pause operation double bandwidth/ h/w support for full duplex flow control ? long/short packet mode ? pad generation mac : media access control ric : repeater ic mii : media independent interface cam : content addressable memory
electronics 16 may 98 lsi division KS32C5000 100/10mbps ethernet controller transmit block flow control receive block mac transmit buffer mac receive buffer address cam mac control & status bdma transmit buffer bdma controller bdma receive buffer s y s t e m b u s b d i i m i i / 10 m b p s 7 w i r e media dependent interface 32 8 bdma & system bus interface mac layer physical layer
electronics 17 may 98 lsi division KS32C5000 hdlc (block diagram) dma controller bus controller hdlc control & status registers tx fifo (8 word) rx fifo (8 word) fcs generator flag/ abort/ idle generator & transmitter receive shift register fcs checker zero insertion flag/ abort/ idle detection zero deletion dpll brg s y s t e m b u s r e m o t e s e r i a l p o r t encoder decoder control data rxd txd dpll_clk autoecho loop brg_clk dplloutr dplloutt brgout1 brgout2 brgout3
electronics 18 may 98 lsi division KS32C5000 hdlc ? protocol features z flag detection and synchronization z zero insertion and deletion z idle detection and transmission z fcs encoding and detection(16-bit) z abort detection and transmission ? address search mode ? no-crc mode ? automatic crc generator preset ? digital pll block for clock recovery ? baud rate generator ? nrz/nrzi/fm/manchester data formats for tx/rx ? loop-back and auto echo mode ? selectable 1-word or 4-word data transfer mode ? tx and rx fifos 8-word depth ? data alignment logic ? endian translation ? programmable interrupts ? modem interface ? up to 4mbps using external receive clock ? up to 2mbps with 32mhz mclk for fm encoding using dpll ? up to 1mbps with 32mhz mclk for nrzi encoding using dpll ? 2-ch dma controller z 2-ch for htxfifo and hrxfifo z 4-word burst transfer mode z count for counting transferred bytes from hrxfifo to memory ? hdlc frame length based on octets
electronics 19 may 98 lsi division KS32C5000 unified cache ? 8k byte ( 2048 instructions or data /32, 4096 instruction or data /16) ? 2 way set associative ? single cycle access ? can define two non-cacheable regions for data only ? main memory updated by write through four write buffers ? software/hardware selectable for cache disable cpu s-arm7t copies of instruction copies of data cache address instructions and data instructions data memory address instructions and data
electronics 20 may 98 lsi division KS32C5000 timers ? two 32-bit programmable timers ? operate in toggle mode and interval mode ? an interrupt request is generated whenever the timer count out(down count) timer data register timer count register (down counter) pnd pulse generator interval mode toggle mode interrupt request auto reload mclk
electronics 21 may 98 lsi division KS32C5000 dma ? two general dma channels memory-from/to-memory serial port(uart)-from/to-memory ? dma operation can be triggered by s/w and/or by external dma requests ? operation can also be stopped and then restarted by s/w ? s/w polling and/or internal dma interrupt can be used to recognize the completed dma operation ? 8,16,and 32bit data transfers ? address can be generated to big endian format dma0 dma1 ndreq0 ndreq1 ndack0 ndack1 system bus nxdack nxdreq0 uart0 uart1 nxdreq1 mode selection
electronics 22 may 98 lsi division KS32C5000 uart ? two independent channels ? dma or interrupt based operation ? 5-, 6-, 7-, or 8-bit data to be transmitted or received per frame ? parity mode: none, odd, even, parity forced/checked 1, 0 ? programmable baud rate z baud rate = baud clock / (divisor x 16) ? support ir (infra-red) tx/rx : irda(infra- red data acquisition) z in ir mode, the tx period is pulsed at a rate of 3/16 that of the normal tx rate(when thr = 0) ? loop back mode for testing the uart uart block txd irs rxd re ir tx encoder ir rx decoder txd rxd 0 1 0 1
electronics 23 may 98 lsi division KS32C5000 i/o (input/output) & interrupt ? i/o (input / output) z 18 programmable i/o ports z each pin can be configured individually as input/output or i/o for a dedicated signal ? interrupt z 20 source 4 external 16 internal z normal or fast interrupt modes irq (interrupt request) fiq (fast interrupt request) z prioritized interrupt handling

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